Round-trip latency prediction for memory access fairness in mesh-based many-core architectures

Adding shared memory parallelism to FLASH for many-core architectures

In this paper we discuss evolutionary changes to FLASH to enable enhanced applications to run efficiently on both the current generation BG/P and the next generation BG/Q. We motivate the need for change by discussing current FLASH applications and the challenges they are facing on today’s architectures. Our solution to current challenges with a view to the next generation is mixed-mode MPI+Ope...

Establishment of Upper Bounds for Internet Round Trip Message Latency

In this paper, we introduce a framework which can be used for establishing an upper bound on message latency, suitable for construction of Internet-based partially synchronous overlay networks. We propose two network filters for estimating the network states and implement them along with the five other network estimators proposed by other researchers. We monitor various Internet paths by measur...

Memory Optimization in Codelet Execution Model on Many-core Architectures

The upcoming exa-scale era requires a parallel program execution model capable of achieving scalability, productivity, energy efficiency, and resiliency. The codelet model is a fine-grained dataflow-inspired execution model which is the focus of several tera-scale and exa-scale studies such as DARPA’s UHPC, DOE’s X-Stack, and the European TERAFLUX projects. Current codelet implementations aim t...

Many Core Hardware Architectures

A latency simulator for many-core systems

In this paper we present MCoreSim, an open-source simulation framework for massively parallel and many-core computing systems based on OMNeT++. The simulator supports tile-based architectures with distributed memory and meshbased interconnects. Its primary purpose is to allow for investigations on the impact of the heterogeneous in-chip communication latencies, as arising due to the network-on-...